1. Field of the Invention
The present invention relates to a semiconductor device having a multilayer wiring structure formed by a dual damascene method.
2. Description of Related Art
FIG. 2 shows a technique related to a semiconductor device having a multilayer wiring structure as a related art. FIG. 2 shows a cross sectional view of a semiconductor device having a local wiring layer 151 and a power wiring layer 153. Elements such as transistors, not shown, are formed on a semiconductor substrate 101 and on the surface are provided the local wiring layer 151 and the power wiring layer 153. Each of the local wiring layer 151 and the power wiring layer 153 has a dual damascene wiring structure, in which no stopper is provided at the phase boundary between a via layer and a wiring layer (hereinafter, this structure is referred to as the stopper-less structure). The via layer means a layer that includes an interlayer insulation film provided with vias. The wiring layer means a layer that includes an interlayer insulation film provided with wiring grooves.
FIG. 3 shows another example of the semiconductor device of a related art. FIG. 3 shows a dual damascene wiring structure, in which each layer in each of the local wiring layer 151 and the power wiring layer 153 has a stopper layer (106, 114, 124, 134, and 144). Each of those stopper layers functions as an etching stopper at the phase boundary between a via layer and a wiring layer. The dual damascene wiring structure like that is also disclosed in, for example, the patent document (Japanese Unexamined Patent Application Publication No. 2000-349150). According to the patent document, when a wiring pattern is transferred and a wiring groove is formed by etching, a stopper layer controls the depth of the object wiring.
On the other hand, each of the non-patent documents 1 to 3 discloses a structure having a wiring layer of such a dual damascene structure, in which a stopper layer is formed in a local wiring layer and no stopper layer is formed in a power wiring layer.
[Non-patent document 1] High Performance K=2.5 ULK Backend Solution Using an Improved TFHM Architecture, Extendable to the 45 nm Technology Node, R. Fox et al., Technical Digest 2005 IEDM
[Non-patent document 2] A Cost-Effective Low Power Platform for the 45-nm Technology Node, E. Josse et al., 2006, Technical Digest 2006 IEDM
[Non-patent document 3] Advanced 300 mm Cu/CVD LK (k=2.2) Multilevel Damascene Integration for 90/65 nm Generation BEOL Interconnect Technologies, L. P. Li et al., Technical paper 2003 Symposium on VLSI Technology